Through Silicon Via Stress Characterization Essay

MDPI and ACS Style

Sun, F.-L.; Liu, Z.-Q.; Li, C.-F.; Zhu, Q.-S.; Zhang, H.; Suganuma, K. Bottom–Up Electrodeposition of Large-Scale Nanotwinned Copper within 3D Through Silicon Via. Materials2018, 11, 319.

AMA Style

Sun F-L, Liu Z-Q, Li C-F, Zhu Q-S, Zhang H, Suganuma K. Bottom–Up Electrodeposition of Large-Scale Nanotwinned Copper within 3D Through Silicon Via. Materials. 2018; 11(2):319.

Chicago/Turabian Style

Sun, Fu-Long; Liu, Zhi-Quan; Li, Cai-Fu; Zhu, Qing-Sheng; Zhang, Hao; Suganuma, Katsuaki. 2018. "Bottom–Up Electrodeposition of Large-Scale Nanotwinned Copper within 3D Through Silicon Via." Materials 11, no. 2: 319.

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1. Introduction

As semiconductor technology scaling becomes increasingly difficult, 3D stacking has recently gained attention due to its potential to offer much higher form factor along with higher performance and lower power compared to 2D designs. 3D stacking can be achieved in many different ways: package-to-package stack, die-to-die stack, die-to-wafer stack, and wafer-to-wafer stack. Package-to-package stack and die-to-die stack allow selection of known good dies for stacking and, thus, provide higher yield but limited performance improvement compared to 2D. In addition, these have higher cost as each die needs to be handled individually while building a stacked module [1,2,3]. The through-silicon-via (TSVs) used in package and die level stacks are typically larger in size thereby limiting the bandwidth and performance offered by these. On the other end, wafer-to-wafer 3D stack allows TSVs to be scaled by 20 times thereby allowing much higher bandwidth and performance improvement along with lowest manufacturing cost by allowing stacking of wafers instead of chip and thereby supporting volume production. However wafer-stacking technology can potentially suffer from compounded yield loss, but this can be mitigated by the use of innovative circuit design, fault tolerant and repair techniques. Due to the strong consumer demand for higher performance in a smaller size with lower cost 3D technology, the industry is moving towards wafer level stacked technology.

The scaling of TSVs depends on the aspect ratio (DTSV/TSi) of TSV diameter (DTSV) to thickness of silicon (TSi), which in turn is governed by techniques used to etch, deposit the oxide and plating of TSVs. Thus silicon thickness must scale with TSV diameter for fixed aspect ratio. Handling of thin die is more difficult than handling of thin wafers and thus wafer stacking supports smaller TSVs and TSV keep out, and much higher 3D connection density thereby allowing much higher bandwidths. Also, by allowing TSVs to directly land on a wiring level, the need of micro-pillars for 3D communication is eliminated in wafer stacking, thereby overcoming the limitation imposed by limited scaling of micro-pillar pitch, and, thus, favoring further scaling of TSV pitch that supports higher bandwidth.

Two key applications for wafer stacking are envisioned to be (a) massively parallel simple cores; (b) scaling of commodity memory. The increasing cost of lithography, and reliability and yield issues associated with the scaling of technology have made the cost reduction with scaling of technology node very difficult. Wafer scale 3D stacking allows scaling with existing technology nodes. Prior work [3] has presented wafer-scale integration with tungsten TSV for low-power applications.

In this paper we present the stacking of high performance POWER7™ cache cores [4] in 45 nm SOI technology with EDRAM and 13 metal levels. Five micrometer diameter electrically isolated Cu TSVs at 13 µm pitch are used for power delivery and signal communication in the stacked cache cores. Wafers are aligned and joined using low temperature oxide bonding after nine levels of metals. The wafers are thinned to 13 µm using grind polish and etch. TSVs are defined post bonding and thinning using conventional alignment techniques. Up to four additional metal levels are formed post bonding and TSV definition.

The remainder of this paper is organized as follows: Section 2 provides a review of the existing methods for wafer-scale bonding along with a comparison of how the existing methods differ from our method of oxide bonding. The details of our wafer stacking 3D technology and process flow are described in Section 3. Section 4 describes the hardware test results and analysis. Finally, conclusions are presented in Section 5.

2. Previous Work

Wafer-scale bonding can yield important benefits with respect to 3D integration. Among these are micro-scale interconnects (IC) with lower IC delay, very high data bandwidth due to the tighter possible IC pitch, and lower power consumption. In addition, very high throughput is achievable as multiple chips are bonded in parallel fashion and singulated later. As a result, cost savings and high-volume manufacturing can be achieved. With minimal modifications and additions to current manufacturing infrastructure, wafer-scale integration is possible, provided a suitable bonding approach is selected. There are several options regarding the wafer bonding approach, several of which are discussed below.

2.1. Metal-Metal Bonding

This process utilizes metal micro-bumps or pillars/studs on the bonding surface of each wafer and subsequent wafer bonding and it establishes direct electrical connection between the two wafers. There are various methods for achieving the formation of the metallic protrusions that can be used for this. The well-known method of using C4 interconnects, typically used in chip packaging, is not suitable for multiple wafer stacking due to thermal budget limitations and the large size of C4s, which limits bandwidth [5]. Therefore, alternative methods have been considered, as described below.

One example is Au/Sn soldering, which involves micro-bump formation. This utilizes the eutectic compositions of the Au/Sn metallurgy [6]. Such an approach can have some important advantages besides direct electrical connection, such as low soldering temperature, self-aligning during bonding, very good wetting behavior, adequate corrosion resistance, etc. However, it may suffer from mechanical stability issues and typically requires under fill processes to ensure mechanical robustness, which increases cost and complexity. In addition, the alignment performance and scaling of interconnections critical dimension (CD) and pitch can be much more challenging, as it is limited by the dimensions of the micro-bumps and throughput may also be a concern.

Another metal-metal wafer bonding method involves the use of solid-liquid inter diffusion (SLID) bonding. In this case, a higher melting point metal (i.e., Cu) is combined with a lower melting point metal (i.e., Sn) [7]. The key in this case is to place the lower melting point metal between the higher melting point metal pads/studs/pillars. Once such structures are created, a thermal compression step is applied in order to facilitate the melting of the low meting point metal and its diffusion into the higher melting point metal with which it forms inter-metallic states. This technique has similar overall advantages and disadvantages to the soldering described above. However, it suffers from limited scalability for multi-wafer stacking due to the limited thermal stability of the bonds vs. what is needed for further wafer processing.

Metal-metal thermal compression bonding is a somewhat more promising case for wafer-scale bonding compared to the ones above. In this method, the metal structures (i.e., Cu micro studs/pillars) typically protrude out of the dielectric surface from the wafer surface, usually due to a recess process for the dielectric [8]. It is critical to prevent corrosion and create clean metal surfaces prior to bonding, therefore special clean processes that remove the oxide and other impurities are used to prepare the surface of the wafers. This approach has the advantage of direct electrical connection and the high bond energy of the metal-metal bond interfaces. However, this also typically requires under fill to address mechanical stability and reliability concerns, which increases cost and complexity. The bonding overlay/alignment performance on a wafer-scale needs to be very accurate, especially for small CD interconnect features. In addition, scaling of interconnections CD and pitch can be more challenging vs.

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